1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing dynamic random access memory (DRAM) capable of reducing leakage current at junctions.
2. Description of the Related Art
In this information age, dynamic random access memory (DRAM) has become an indispensable component in many electronic products. As more memory capacity is demanded for each DRAM chip, the size of each DRAM device must decrease correspondingly.
To increase the density of DRAM devices, dimensions of each memory cell must decrease. However, reducing the dimensions of a DRAM cell also reduces the size of the capacitor within the memory unit, and hence is likely to reduce the capacitance of the capacitor. A lowered capacitance leads to a faster data loss resulting from an increase in charge leakage through an internal decay mechanism. Because the charges inside a DRAM storage capacitor leak out continuously, the DRAM storage capacitor must be refreshed from time to time to replenish charges. The frequency of refreshing is inversely proportional to capacitance of the capacitor. Because read or write operation cannot be carried out during a refreshing cycle, performance of the DRAM device eventually drops. Therefore, a method capable of producing a high-density and high performance DRAM device with a high capacitance capacitor and low level leakage is required.
Conventionally, the steps for producing DRAM includes forming shallow trench isolation (STI) structures in a substrate to mark out the active regions of memory cells, and then forming transistors in the active regions. After an isolating dielectric layer is formed over the transistors, bit line contact openings are formed in the dielectric layer. Bit lines that connect electrically with the respective transistor terminals through the bit contact openings are formed over the dielectric layer. After the formation of a second dielectric layer over the bit lines, node contact openings are formed and pass through the two dielectric layers. Finally, capacitors that connect electrically with the terminals of the respective transistors through the node contact openings are formed over the second dielectric layer.
In a conventional process of forming the DRAM device, internal stresses are likely to form when the STI structures are created. Dislocations and defects within the active regions of the semiconductor substrate can result in unwanted leakage current at junctions. In addition, since the concentration of dopants in the source/drain regions of the transistors is relatively high and reaches considerable depth and width, parasitic capacitance is usually high, thereby leading to an intensification of junction leakage current. Hence, the DRAM capacitors have to be refreshed more often.
In the meantime, due to the increase in level of device integration and reduction in line width, misalignment of contact opening now occurs more frequently, leading to a shift in contact position. Consequently, a portion of the charges in the node electrode moves towards the substrate, leading to the production of a leakage current and possibly device malfunction. To prevent the adverse effects of misalignment, stricter design rules must therefore be formulated.